Mahoney & Lyle

Company Revolutionizes Power Conversion With Cutting-Edge Digital Control and Advanced GaN Devices Serving Fast-Growing Markets, Such as Data Centers and EVs

Hyeres, France – Sept. 8, 2025 – Wise Integration, a pioneer in digital control for gallium nitride (GaN) and GaN IC-based power supplies, today announced the appointment of Ghislain Kaiser as Chief Executive Officer. Kaiser succeeds CEO and co-founder, Thierry Bouchet, who will continue to serve as Chief Technology Officer and General Manager, leading the worldwide R&D and driving the technological vision. 

A seasoned high-tech leader with a proven track record in growing and leading global teams in the semiconductor industry, Kaiser brings deep experience in scaling deep-tech ventures. In 2006, he cofounded Docea Power, a French EDA startup pioneering full-chip, system-level power and thermal modelling, with the vision of addressing the growing power-consumption and thermal challenges in IC and platform design.

As CEO, he led the company to domain leadership and its acquisition by Intel in 2015. He then joined Intel, where for the next decade he held senior director roles, most recently overseeing system-simulation engineering and worldwide customer-enablement organization. Those programs tackled the most critical power, thermal, and performance challenges in designing consumer, data-center, and AI systems. Kaiser began his career at STMicroelectronics, where he held technical and leadership positions across test and product engineering, design, and architecture teams.

Targeting Fast-Growing Markets

With Kaiser’s appointment, Wise Integration is positioning itself to scale globally and capitalize on booming markets such as data centers powering  artificial intelligence (AI), and  electric vehicles (EV)— which demand more efficient, compact, and digitally controlled power architectures.

“I’m thrilled to join Wise Integration and build on its success in providing customers differentiated solutions in power electronics to meet their biggest challenges,” Kaiser said. “This talented team has created an R&D-driven culture and a robust foundation to lead the GaN power electronics transformation globally.”

The Next Chapter

“On behalf of the board of directors, I am pleased to welcome Ghislain Kaiser as Wise Integration’s new CEO, and to compliment the team for their exceptional work,” said Board Chairman Patrick Boulaud. “This marks a major milestone for the company as it transitions from a CEA‑Leti spinout into a pioneering force in GaN and digital power management innovation with strong growth potential. Ghislain’s background makes him a natural choice as the CEO to guide the company through this next stage of growth.”  

“Ghislain’s arrival begins a new chapter for Wise Integration,” Bouchet added. “With our WiseGan® devices and WiseWare® digital control, we’ve built a strong foundation in consumer markets. Now it’s time to scale our innovations and tackle the next big challenges—bringing unmatched efficiency and power density to AI servers, data centers, and tomorrow’s automotive systems.”

Selected Highlights (2020–2025)

• Spun out from CEA‑Leti in 2020 using the institute’s GaN-on-silicon R&D platform
• Developed proprietary WiseGan® IC and WiseWare® microcontroller
• Launched its fully digital controller, WiseWare® 1.1
• Opened a design center in Canada and established an Asian subsidiary in Hong Kong

About Wise Integration

Wise Integration is a fabless company founded in France in 2020, specializing in advancing power electronics through innovative GaN technology and digital control solutions. Leveraging its expertise, the company introduced a breakthrough synergy between its GaN device (WiseGan®) and a fully digital controller, WiseWare®. This powerful combination enables development of technologies facilitating power supplies that are up to 3x smaller, 3x more efficient, and 3x lighter than traditional chargers. Targeting a broad spectrum of markets, including consumer electronics, e-mobility, industrial applications, artificial intelligence data centers and automotive, Wise Integration is an industry leader at transforming power delivery with its cutting-edge components and digital control technologies.

Headquartered in Hyeres, France, the company operates a design center in Ottawa, Ontario, Canada, and an R&D center in Grenoble, France. Its Asian subsidiary, Wise Integration Ltd., is based in Hong Kong, and it has offices in Taiwan and South Korea.

For more information, visit www.wise-integration.com

Wise Integration Press Contact                                                                       Sarah-Lyle Dampoux                                                                             +33 6 74 93 23 47                                                                     sldampoux@mahoneylyle.com                                                            

With WiseWare® 1.1, GaN-Based Designs Achieve Compact Size and Peak Efficiency

Hyeres, France – June 26, 2025 – Wise Integration, a pioneer in digital control for gallium nitride (GaN) and GaN IC-based power supplies, today announced the release to production of its first fully digital controller, WiseWare 1.1 (WIW1101) based on the MCU 32 bits. This milestone innovation enables high-frequency operation up to 2 MHz, unlocking new levels of power density, efficiency, and form factor in compact AC-DC power converters.

The product is now available and ready for volume production in customer-validated designs.

“This release marks a strategic milestone for Wise Integration’s roadmap,” said Thierry Bouchet, CEO of Wise Integration. “WiseWare 1.1 represents more than a product—it’s a key pillar in our vision to redefine power electronics through digital control. It strengthens our value proposition in high-density power conversion and reinforces our leadership as GaN technology scales to mass adoption.”

Digitally Driven, GaN Optimized

Unlike legacy analog solutions, WiseWare 1.1 leverages the speed and switching capabilities of GaN (gallium nitride) through a proprietary digital control algorithm in a MCU 32 bits, that enables zero voltage switching (ZVS) across all power transistors. Designed specifically for totem pole power-factor correction (PFC) architectures in critical-construction mode (CrCM), this controller allows engineers to dramatically reduce the size, weight, and thickness of magnetic components while maintaining >98 percent efficiency.

Customer-Proven Performance and Global Momentum

WiseWare 1.1 supports a broad power range from 100 W to 1.5 kW, making it suitable for a wide array of modern applications requiring both compactness and high energy efficiency.

Designed with flexibility in mind, WiseWare 1.1 works seamlessly with standard GaN across the full RDS(on) spectrum (drain-source on-resistance), giving power designers the freedom to choose the optimal transistor for each application—without compromising performance.

Typical applications include:

• High-efficiency AC-DC power converters,
• High-power density designs,
• Power supplies for servers,
• USB power delivery adapters for laptops and notebooks, and
• Switch-mode power supplies for monitors and displays.

The WiseWare 1.1 platform has already demonstrated robust market validation, with multiple customer design-ins and live demos at PCIM Europe, one of the industry’s most prominent power- electronics exhibitions. These demonstrations showcased 300W totem pole PFC converter boards using WiseWare 1.1 and WiseGan® WI71060A transistors (RDS(on)=60mohms), operating from 90–264 VAC input to a 400 VDC output. At the same time, technical collaborations are progressing in Asia, reinforcing the company’s global reach.

Technical Highlights of WiseWare 1.1 (WIW1101)

• Switching frequency: up to 2 MHz
• Control mode: CrCM ensuring full ZVS
• Integrated protections: OCP, OVP, OTP, OPP
• Inrush management: no need for relay or thermistor
• Standby power: as low as 18 mW
• EMC-compliant demoboard with >98 percent efficiency

About Wise Integration

Wise Integration is a French fabless company founded in 2020, specializing in the advancement of power electronics through innovative GaN technology and digital control solutions. Leveraging its expertise, Wise Integration introduces a compelling synergy between its GaN device (WiseGan®) and a 32-bit, MCU-based, AC-DC digital controller (WiseWare®). This powerful combination enables the development of technologies facilitating chargers that are up to 3x smaller, 3x more efficient and 3x lighter, catering to power requirements from 30W to 7kW. Targeting a broad spectrum of markets, including consumer electronics, e-mobility, industrial applications, data centers and automotive sectors, Wise Integration is at the forefront of transforming power delivery with its cutting-edge components and digital control technologies. 

Headquartered in Hyeres, France, the company has a North American Design & Development Center in Ottawa, Ontario, Canada, and an Asian subsidiary, Wise Integration Ltd., based in Hong Kong.

For more information, visit www.wise-integration.com.

Wise Integration Press Contact                                                                        

Sarah-Lyle Dampoux                                                                            

+33 6 74 93 23 47                                                                    

sldampoux@mahoneylyle.com                                                            

Wise Integration Contact

Rym Hamoumou       

Rym.hamoumou@wise-integration.com

Capacity to Deliver Millions of TFLN Chips Annually ‘Firmly Positions Europe as a Global Leader in Photonic Chip Manufacturing’

June 23, 2025 – A recently concluded 42-month EU project, ELENA, announced today the development of the first-ever, European-made lithium niobate on insulator (LNOI) substrates for photonic integrated circuits (PICs)—a breakthrough that establishes a fully European supply chain for thin-film lithium niobate (TFLN) technology.

TFLN is a breakthrough material platform enabling high-performance PICs through its thin-film structure, offering unique electro-optic, nonlinear optical, and acousto-optic properties. The advent of LNOI wafers allows micromachining of LN with high precision, integrating multiple optical functions within a footprint smaller than a fingertip. These attributes make LNOI particularly attractive for high-speed, low-power optical communications and quantum systems.

Until now, the LNOI ecosystem has been constrained by a limited supply chain reliant on a single commercial supplier outside the EU—and the absence of a commercial foundry capable of producing TFLN photonic chips at scale. The ELENA project directly addressed these critical gaps by establishing Europe’s first commercial LNOI wafer supply and laying the groundwork for a TFLN photonic chip foundry.

The €5 million initiative united 10 partners across the PIC value chain—from substrate innovation and photonic design to manufacturing, testing, and packaging. Key outcomes include the first process design kit (PDK) for the LNOI platform and advances in foundry-compatible processes to transition TFLN technology from research to commercial production. This effort significantly enhances European sovereignty in a strategically vital segment of the semiconductor supply chain.

Spinout Launched to Produce TFLN Photonic Chips on 150mm Optical Grade Wafers

A cornerstone of the project is the creation of Europe’s first open-access LNOI photonic chip foundry at the Swiss Center for Electronics and Microtechnology’s (CSEM) certified cleanroom facility in Neuchâtel, Switzerland. There, TFLN chips will be produced on 150 mm optical-grade LNOI wafers at industrial scale. As a result, CSEM, which coordinated the project, has launched CCRAFT, a dedicated spinout to scale up production.

“The spinout foundry is uniquely positioned at the core of the TFLN value chain, because it delivers production-grade service, a rare block in the supply chain,” said Hamed Sattari, ELENA’s project manager and CEO of CCRAFT. “CCRAFT’s roadmap includes expanding capacity to deliver millions of TFLN chips annually, firmly positioning Europe as a global leader in photonic-chip manufacturing.”

The availability of a production-grade photonic chip foundry, combined with project members CEA-Leti and SOITEC’s plans to commercialize LNOI wafers, also supports Europe’s ability to manufacture the next generation of photonic chips across a broad range of markets and industries.

Meeting Diverse Market Needs with Demonstrator Prototypes

To validate the platform, ELENA produced four demonstrator PICs targeting high-impact sectors:
• Quantum: ion trapping, optical clocks, entangled photon generation,
• Telecom: >400 Gbit/s modulators, DWDM, CMOS-compatible transceivers,
• Space: lightweight, low-power PICs for satellite communications, and
• LIDAR/Sensing: compact, efficient systems for automotive, medical, and environmental monitoring.

As demand surges for faster, energy-efficient electro-optic chips across AI, data centers, and telecommunications, ELENA’s achievement firmly positions the EU at the forefront of global photonics innovation.

The partners, which include leading European research institutes, large industrial companies and SMEs (short names in brackets), are:
1) Swiss Center for Electronics and Microtechnology (CSEM), Switzerland;
2) CEA-Leti (Leti), France;
3) SOITEC SA (Soitec), France;
4) VPIphotonics GmbH (VPI), Germany;
5) Eidgenössische Technische Hochschule Zürich (ETHZ), Switzerland;
6) Vanguard Automation GmbH (VA), Germany;
7) Thales SA (THALES), France;
8) III-V LAB (III-V LAB), France;
9) Rosenberger Hochfrequenztechnik GmbH & Co. KG (ROS), Germany; and
10) L-up SAS (LUP), France.


About ELENA
ELENA project is a collaborative research and innovation initiative funded by the European Commission under Horizon 2020 (Grant Agreement n°101016138). It brings together leading European research institutes, large industrial partners and SMEs to establish a complete European supply chain for PICs based on TFLN. ELENA achievements include a fully European supply chain for that technology and establishing Europe as second supplier worldwide of LNOI wafers. Visit ELENA

ELENA & CCRAFT Contacts: contact@elena-project.eu; foundry@ccraft.com
Press Contact
Agency
Sarah-Lyle Dampoux
sldampoux@mahoneylyle.com
+33 6 74 93 23 47

Focus Is on Protecting Critical Markets Such as Automotive, Industrial IoT, and Secure Infrastructure

GRENOBLE, France – June 18, 2025 – CEA-Leti and Soitec today announced a strategic partnership to enhance the cybersecurity of integrated circuits (ICs) through the innovative use of fully depleted silicon-on-insulator (FD-SOI) technologies. This collaboration aims to position FD-SOI as a foundational platform for secure electronics by leveraging and extending its inherent resistance to physical attacks.

At the heart of the initiative is a joint effort to experimentally validate and augment the security benefits of FD-SOI—from the substrate level up to circuit design. The project aims to deliver concrete data, practical demonstrations, and roadmap guidance to meet the surging cybersecurity demands in critical markets such as automotive, industrial IoT, and secure infrastructure.

Combining Expertise to Secure the Future of Electronics

The partnership, which will utilize GlobalFoundries’ advanced chip manufacturing capabilities, will address a growing need for trusted components in embedded and cyber-physical systems—systems that must deliver security services and withstand both software- and hardware-level attacks. With FD-SOI’s proven advantages against laser fault injection (LFI) attacks due to its thin-film architecture and channel isolation, the technology presents a compelling foundation for next-generation secure IC design.

Key goals of the partnership include:

• Highlighting FD-SOI’s existing strengths in cybersecurity.
• Co-developing innovations across the substrate-design stack to boost physical robustness and meet security requirements in automotive and other embedded systems.
• Demonstrating empirical security data to reinforce FD-SOI’s credibility in certification contexts such as SESIP and Common Criteria.

Context: Rising Threats, Rising Demand

“In an era marked by increasing attacks on connected systems and autonomous vehicles, the need for embedded hardware capable of resisting physical tampering has never been greater,” said CEA-Leti CTO Jean-René Lequepeys. “FD-SOI’s unique combination of performance, energy efficiency, and attack resistance offers an ideal answer for industries that demand both trust and efficiency. This project will leverage research results from the FAMES Pilot Line.”

FD-SOI’s critical benefits include:

• Physical attack resistance, enabled by electrical isolation between the channel and substrate.
• Power-performance optimization, vital for battery-constrained applications like automotive ECUs and industrial sensors.
• Security design enablement, allowing tailored countermeasures such as fault detection and isolation of sensitive circuit domains.

Long-Term Vision: Toward a New Cyber-Substrate

While the initial phase focuses on leveraging existing FD-SOI capabilities, the project sets the stage for long-term innovation. The envisioned next-generation cyber-substrate would expand upon FD-SOI’s strengths by incorporating:

• Enhanced protection against backside and invasive physical attacks.
• Embedded anti-tamper features and physical unclonable functions (PUFs) for hardware fingerprinting.
• Dynamic response mechanisms to detect and counter emerging threats.

This future-oriented work will address both cyber and supply-chain vulnerabilities—making FD-SOI not only more secure, but also more indispensable.

“Our goal is to raise awareness of FD-SOI as a trusted technology platform and to collaboratively explore innovations that will strengthen physical resistance against emerging attack vectors,” said Christophe Maleville, CTO and senior executive vice president of Soitec’s innovation[JM1] . “The development of a new substrate may be part of longer-term prospects, while the initial focus is to leverage existing FD-SOI capabilities and provide experimental validation of their value for secure systems.”

For more information: https://www.soitec.com/en/ and follow us on LinkedIn and X: @Soitec_Official

Media Relations: media@soitec.com

Press Contact                                                                                                                         

Agency Sarah-Lyle Dampoux sldampoux@mahoneylyle.com +33 6 74 93 23 47

About CEA-Leti (France)

CEA-Leti, a technology research institute at CEA, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, CEA-Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. CEA-Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, CEA-Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 2,000 talents, a portfolio of 3,200 patents, 11,000 sq. meters of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley, Brussels and Tokyo. CEA-Leti has launched 76 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

Technological expertise

CEA has a key role in transferring scientific knowledge and innovation from research to industry. This high-level technological research is carried out in particular in electronic and integrated systems, from microscale to nanoscale. It has a wide range of industrial applications in the fields of transport, health, safety and telecommunications, contributing to the creation of high-quality and competitive products.

For more information: www.cea.fr/english 

About Soitec

Soitec (Euronext – Tech Leaders), a world leader in innovative semiconductor materials, has been developing cutting-edge products delivering both technological performance and energy efficiency for over 30 years. From its global headquarters in France, Soitec is expanding internationally with its unique solutions, and generated sales of 0.9 billion Euros in fiscal year 2024-2025. Soitec occupies a key position in the semiconductor value chain, serving three main strategic markets: Mobile Communications, Automotive and Industrial, and Edge and Cloud AI. The company relies on the talent and diversity of its 2,300 employees, representing 50 different nationalities, working at its sites in Europe, the United States and Asia. Soitec has registered over 4,000 patents.

Soitec, SmartSiC™ and Smart Cut™ are registered trademarks of Soitec.

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58 Partners Charged with Implementing Cutting-Edge Solutions For Emission Control, Materials Innovation, Waste Reduction, & Raw Material Reuse

GRENOBLE, France – June 6, 2025 – A pan-European consortium dedicated to developing sustainable processes and technologies for the semiconductor-manufacturing industry today announced the launch of the GENESIS project. This integrated, large-scale initiative aims to enable Europe’s chip industry to meet its sustainability goals—from materials development to final waste treatment.

Coordinated by CEA-Leti, the three-year project brings together 58 partners spanning the entire European semiconductor value chain, from large enterprises and SMEs to research institutes, universities, and industry associations. GENESIS will drive innovative solutions in emission control, eco-friendly materials such as alternatives to PFAS-based ones, waste minimization, and raw material reuse, directly aligned with the European Green Deal and European Chips Act.

“GENESIS is designed to address the complex challenges of building a truly sustainable semiconductor ecosystem,” said Laurent Pain, Sustainable Electronics Program director at CEA-Leti. “Its structure reflects both the urgency and the opportunity of Europe’s green transition, powered by the complementary expertise and close collaboration of its partners.”

45 Sustainability Innovations Driven by Four Strategic Pillars

Pain, manager of the project, noted that the team expects to deliver approximately 45 sustainability-driven innovations covering the semiconductor lifecycle, guided by four strategic pillars that form the technological foundation of GENESIS’s vision for a green European semiconductor industry:

• Pillar 1 – Monitoring & Sensing: Real-time emissions tracking, traceability, and process feedback systems,

• Pillar 2 – New Materials: PFAS-free chemistries and low-GWP alternatives for advanced semiconductor processes,
• Pillar 3 – Waste Minimization: Innovations in recycling (solvent, gas, slurries), reuse, and sustainable replacements, and
• Pillar 4 – Critical Raw Materials Mitigation: Strategies to reduce dependency on CRM and strengthen resource security.

Complimenting these pillars, the project’s objectives establish an overall framework that includes deploying sensor-integrated abatement systems to reduce PFAS and GHG emissions. It also aims to position Europe as a leader in green semiconductor innovation by aligning supply-chain practices with environmental regulations.

A Green Fit for Europe’s Chips Agenda

“The launch of the GENESIS project marks a critical step toward aligning Europe’s semiconductor ambitions with its climate commitments,” said Anton Chichkov, head of programs at Chips Joint Undertaking (Chips JU), a public-private partnership created to bolster Europe’s semiconductor industry by fostering collaboration between the EU, member states, and the private sector.

“As chips become the backbone of everything from AI to energy systems, their environmental footprint is rapidly growing,” he said. “GENESIS responds to this urgent challenge by pioneering sustainable alternatives in materials, waste reduction, and resource efficiency. Through this initiative, Europe is not only investing in cleaner technologies—it’s positioning itself as a global leader in green semiconductor manufacturing.”

With a budget of close to €55 million, the GENESIS project is co-funded through the Chips Joint Undertaking by the European Commission, participating EU member states, and the Swiss State Secretariat for Education, Research and Innovation (SERI).

About GENESIS

GENESIS (GENErate a Sustainable Industry for Semiconductors) is a pan-European project co-funded by the EU, Chips JU, Member States, and the Swiss State Secretariat for Education, Research and Innovation (SERI). Coordinated by CEA-Leti, it includes 58 partners from across Europe, focused on leading semiconductor manufacturing into a circular economymodel, which aims to minimize waste and maximize resource reuse, and a low-impact, innovation-driven industry. https://www.genesiseu.eu/

About CEA-Leti (France)

CEA-Leti, a technology research institute at CEA, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, CEA-Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. CEA-Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, CEA-Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 2,000 talents, a portfolio of 3,200 patents, 11,000 sq. meters of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley, Brussels, Tokyo, Taipei, Taiwan, and Seoul, South Korea. CEA-Leti has launched 80 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

Technological expertise

CEA has a key role in transferring scientific knowledge and innovation from research to industry. This high-level technological research is carried out in particular in electronic and integrated systems, from microscale to nanoscale. It has a wide range of industrial applications in the fields of transport, health, safety and telecommunications, contributing to the creation of high-quality and competitive products.

For more information: www.cea.fr/english

Press Contact  Agency Sarah-Lyle Dampoux sldampoux@mahoneylyle.com +33 6 74 93 23 47

Workshop at CEA-Leti Innovation Days—LID World Summit Begins an Extended Series Of Courses and Training to ‘Shape the Future’ of Europe’s Chip Design and Integration

GRENOBLE, France – June 6, 2025 – The FAMES Pilot Line today announced the official launch of the FAMES Academy, a strategic educational initiative designed to support the EU’s commitment to develop next-generation  chips. The academy will be unveiled during CEA–Leti Innovation Days—LID World Summit, June 17-19, beginning with its inaugural workshop on June 18 in Grenoble.

Through a series of dedicated training events, courses, and workshops over the next four years, the FAMES Academy aims to support and expand a skilled workforce equipped to use the advanced technologies developed within the FAMES Pilot Line—key enablers for the European Chips Act and European chip sovereignty.

“The FAMES Academy is a cornerstone of our mission to equip Europe’s microelectronics community with the skills needed to leverage FD-SOI technology and design circuits using advanced setups,” said Laurent Fesquet, FAMES Academy project manager. Fesquet, who will lead a panel discussion at the workshop, is deputy director of the TIMA Laboratory (UGA – Grenoble INP – CNRS). “Through recruitment and targeted training, we’re preparing the engineers and technicians who will shape the future of Europe’s semiconductor design and integration,” he said.

Kickoff Events to Cultivate Cutting-Edge Competencies

The June 18 event will explain the technologies that will be covered in the academy’s ongoing training program. It will feature a morning general session, followed by an afternoon workshop that is part of the academy’s formal training program. This will be the first in a series of workshops and training sessions over the next four years, providing professionals from industry, RTOs, and academia with hands-on opportunities to engage with groundbreaking FD-SOI, eNVM, RF, 3D integration, and PMIC technologies.

The second major academy event will be the FAMES European FD-SOI Design School (EFDS), Jan. 25-30[JM1] , 2026, in Grenoble. This winter school will feature a one week theoretical and practical training course. Additional events include a two-day course at the Tyndall Institute in Cork, Ireland, Nov. 24-25, 2025, as well as ongoing tutorials (e-learning) that the academy will offer.

Meeting Industry Needs: A European Commitment to Education

The FAMES Academy will be focused on three critical objectives:

• Supporting the transfer of competencies to European industry to exploit next-generation semiconductor technologies.
• Attracting scientists and engineers into the EU microelectronics workforce to reinforce technological sovereignty.
• Equipping engineers and researchers with the expertise required to design and characterize advanced semiconductor nodes.

Training for a Technological Leap: What to Expect

FAMES Academy participants will gain insights into the trade-offs between integrated circuit performance and power consumption, especially relevant to the automotive, AI, and HPC sectors. Courses will also explore 3D heterogeneous integration, enabling enhanced functionality, performance, and cost optimization through the combination of chips and dies.

The academy’s hands-on training complements the FAMES Open-Access platform, offering users access not just to cleanrooms and equipment, but also to the knowledge required to effectively leverage them. Following the recently completed, first open-access call to submit project proposals, the FAMES Pilot Line is now accepting Spontaneous User Requests.

“Over the next four years, the academy will develop and present a range of workshops and interactive sessions to support and expand Europe’s semiconductor community with expertise and empower its industrial and academic communities with the tools and training needed to succeed in this critical, rapidly evolving field,” said Dominique Noguet, the FAMES Pilot Line coordinator.

A European Collaboration for Chip Sovereignty

In addition  to the pilot line coordinator, France-based CEA-Leti,  the FAMES consortium includes imec (Belgium), Fraunhofer (Germany), Tyndall (Ireland), VTT (Finland), CEZAMAT WUT (Poland), UCLouvain (Belgium), Silicon Austria Labs (Austria), SiNANO Institute (France), Grenoble INP (France) and the University of Granada (Spain).

For further information about training opportunities and upcoming workshops, visit: https://fames-pilot-line.eu/training/

Press Contact Sarah-Lyle Dampoux sldampoux@mahoneylyle.com +33 6 74 93 23 47

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SAN FRANCISCO – Feb. 19, 2025 – Researchers at University of California San Diego (UC San Diego) and CEA-Leti today unveiled a groundbreaking microactuator driving system, combining innovative solid-state battery technology with novel integrated circuit designs for 2-in-1 storage and voltage boost conversion techniques.

Presented in a paper at ISSCC 2025, “An Autonomous and Lightweight Microactuator Driving System Using Flying Solid-State Batteries”, the breakthrough addresses a critical challenge in powering micro-actuators: delivering high voltages (tens to hundreds of volts) efficiently in a lightweight, compact form.

By dividing a solid-state battery – which is already needed in the system – into smaller units and dynamically arranging them, the system achieves high-voltage outputs without traditional bulky components like capacitors or inductors. This results in a highly compact and lightweight design ideal for micro flying robots and embedded medical devices.

“The design uniquely integrates energy storage and voltage conversion, setting a new standard in efficiency and autonomy for small electromechanical actuators. In addition, by leveraging a novel battery matrix, this is the first demonstration of such a system for ultra-low-power, high-voltage applications,” said Gaël Pillonnet, scientific director of CEA-Leti’s Silicon Component Division, and a lead author of the paper.

“Microdrones and microrobotic systems already require a battery, and so it costs us next to nothing to use a solid-state battery, split it up into smaller pieces, and dynamically rearrange the small pieces to generate the voltages we need. This is the smallest and lightest way we could think of to generate the high voltages needed to run these sorts of systems,” said Patrick Mercier, Professor of Electrical and Computer Engineering, co-Director of the Center for Wearable Sensors, and Site Director of the Power Management Integration Center at UC San Diego.

Breakthrough Solid-State Battery Technology

Unlike conventional batteries, which lose energy density when scaled down, the solid-state batteries in this system maintain high energy density even when miniaturized and split into small parts to form a matrix. This enables ultra-lightweight systems with scalable performance. The paper presents a first proof of concept showing up to 56.1V voltage generation capability at up to a few Hz of operating frequency needed by microactuation systems.

The concept has been validated with early commercial solid-state batteries and shows promise for even greater performance using advanced versions developed at CEA-Leti. Extrapolated data indicates that the system can scale down to weights as low as 14mg without sacrificing efficiency, making it a key technology for weight-constrained autonomous robots and small embedded devices for medical applications.

SAN FRANCISCO – Feb. 18, 2025 – CEA-Leti, in its collaboration with Quobly, CEA-List and CEA-Irig, reported today it has developed a unique solution using FD-SOI CMOS technology that provides simultaneous microsecond readouts of tens of quantum devices, while reducing the readout power consumption by 10x and footprint by 2x. Combined with Quobly’s strategy to build qubits out of FD-SOI technology, this readout architecture provides a path to low power and scalable quantum integrated circuits.

In a paper presented at ISSCC 2025, “An 18.5μW/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits”, the innovation is to propose a readout circuit based on a capacitive-feedback transimpedance amplifier (CTIA) that achieves an 18.5μW/qubit power consumption, which is a significant tenfold reduction compared to existing, similar circuits at half the footprint per qubit.

With this circuit, CEA-Leti demonstrated a 4- and 16-point quadrature-amplitude modulation (QAM), that increases the possible number of multiplexed devices by directly using the quantum devices as a modulator.

A capacitive-feedback transimpedance amplifier converts the current coming from the quantum devices into an output voltage. Its gain can be set by adjusting the ratio of the values of the two capacitances of its feedback loop.

The novel system presented minimizes power consumption with a multiplexing strategy that permits measurement of several qubits with one amplifier. This paves the way toward developing the readout of thousands of silicon qubits with a limited number of wires and without the need of bulky inductors, circumventing both the wiring bottleneck and the readout scaling-up limitation of actual cryogenic electronics.

“The silicon qubit is a promising candidate for large-scale, fault-tolerant quantum computing due to its small footprint, higher operating temperature and possible compatibility with industrial CMOS processes,” said Quentin Schmidt, lead author of the paper. “But the need for a simultaneous microsecond readout of thousands of devices is especially challenging in terms of both power consumption and size.”

“This is the first time that as-complex-a-modulation scheme as QAM has been used to address the simultaneous readout of several qubits,” explained Franck Badets, research director of the institute’s Silicon Components Department. “The associated improvements in power efficiency and footprint per qubit for a single amplifier, compared to frequency division multiplexing access state-of-the-art, demonstrated with OOK modulations, open bright perspectives for larger-scale qubit arrays.”

“Quobly’s goal is to fabricate large-scale quantum computers based on silicon. This paper demonstrates key progress toward a scalable readout of the qubits and is a major advance in its roadmap,” explained Tristan Meunier, chief scientist at Quobly, a pioneer in the development of a fault-tolerant quantum computer based on silicon qubits. “Our process, which leverages established FD-SOI technology to benefit from the expertise of the semiconductor industry, is already paying off: This work demonstrates the co-integration of classical electronic functions at low temperature to simultaneously read and control multiple qubits on chip with record low consumption and compact design. Quobly’s partnership with STMicroelectronics, to produce commercial quantum processor units (QPUs) at scale, builds on the ground-breaking work done with CEA-Leti.”

This highly collaborative effort reported at ISSCC was made possible by the unique expertise based in Grenoble. CEA-List offers invaluable guidance to ensure compatibility with future quantum software stacks, while CEA-IRIG provides a one-of-a-kind cryogenic experimental platform. Through their  special partnership with Quobly, all divisions of CEA are positioned to pioneer significant breakthroughs in silicon qubit systems.

CEA-Leti Press Contact                                                                                                          

Agency

Sarah-Lyle Dampoux

sldampoux@mahoneylyle.com

+33 6 74 93 23 47